Machine withOut - of - Order Instruction Completion

1 Project Goal and Overview Our goal in this project is showing that the veriication of complex pipelined machines is possible. As we discussed in the previous sections, the micro-architectural designs of general purpose microprocessors have not been thoroughly studied as a target of formal veriication. It is not clear even how to represent the correctness of the super-scalar super-pipelined machines. Therefore , it is important to discuss what sort of correctness we can represent for processor designs, not only how we can verify it. So it is desirable not to restrict ourselves to a speciic processor design. However, talking about processor designs in general is sometimes diicult and vague. In this paper, we would rather deene a concrete pipelined machine model and discuss its veriication. We believe that our method is not limited to our speciic machine design, and we hope we can reuse our methodology for other processor designs in future projects. Our pipelined machine model tries to capture several interesting features of today's pipelined microprocessor, such as out-of-order execution of instructions, speculative execution and multiple execution units. One of the hardest parts to verify in processor designs is the control logic, so we added a relatively complex issuing logic to our machine design, which stalls the pipeline whenever necessary to prevent data and structural hazards. We want to claim that the veriication of our pipelined machine is much more diicult than a simple DLX pipeline implemation which has little pipeline interlocks, because it is this complexity in